1. Field of the Invention
This invention relates generally to the field of clock holdover circuits and in particular to a circuit for providing a clock signal of a predetermined accuracy upon loss of a reference clock signal.
2. Background Art
In digital data transmission applications, data is typically transmitted as a series of digital bits to a receiver. Accessing the data requires that the receiver be synchronized with the transmitter. Typically, a clocking signal is provided to both the transmitter and receiver to provide such synchronization.
In telecommunication systems, a highly accurate reference clock signal is provided by a central source, such as, for example, a centrally distributed clock within a network, or an available standard such as GPS, Loran, etc. Clock dependant devices receive the reference clock signal and phase lock onto it. As long as the reference is maintained, the dependant device can operate reliably. If the reference is degraded or lost, errors will occur.
In the prior art, a clock holdover circuit is provided to replace the reference clock signal with a local clock signal upon degradation or loss of the reference signal. In one prior art embodiment, a voltage controlled oscillator (VCO) is phase and frequency locked to the reference clock signal. A phase comparator generates an offset voltage level used to provide a control voltage for the VCO so that the output of the circuit matches the input reference clock signal. The offset voltage is coupled to an analog to digital (A/D) converter, converted to a digital word, and stored in a memory. The input reference clock signal is monitored, and if it degrades or is lost, the digital word stored in memory is output to a digital to analog (D/A) converter. The analog output voltage of the D/A converter is coupled to the VCO to provide the proper offset voltage to the VCO so that the input clock signal will match the lost reference clock signal. The memory stores the current valid offset voltage, determined and stored sufficiently prior to the loss of reference to be accurate. When the reference clock signal is available, the system is dynamic, with the offset voltage changing in response to varying conditions within the circuit. When the reference clock signal is lost, the operation of the system becomes static, depending on the current valid stored offset voltage value.
This prior art clock holdover circuit has a number of disadvantages. All the parts involved have characteristics that change as a function of aging and temperature. Additionally, the time and temperature dependencies of the A/D, D/A and VCO are all independent of each other so that over time, the output generated during the clock holdover phase will change as a function of these variables. In telecommunications systems, it is required that this reference clock signal be highly accurate. Due to the time and temperature degradation of the prior art clock holdover circuit, this accuracy is lost when the reference clock signal is unavailable for extended periods of time.
Therefore, it is an object of the present invention to provide a clock holdover circuit which is time and temperature dependencies can be minimized.
It is another object of the present invention to provide a clock holdover circuit which will provide a holdover clocking signal within established tolerances.
It is a further object of the present invention to provide a clock holdover circuit in which circuit variables can be isolated and controlled.